This disclosure relates to re-synchronization of the domain clocks after a low-power or power-down mode to enable fast start-up of a system.
A computer often holds current programs and data in a random access memory (RAM). Each Static RAM (SRAM) bit uses four to six transistors in a dual-stable configuration. This configuration can hold data without external assistance, for as long as power is supplied to the circuit. In contrast, each Dynamic RAM (DRAM) bit uses only one transistor and one capacitor. Hence, the manufacturing cost of the DRAM chips is less than the SRAM chips. However, the DRAM must be refreshed many times per second in order to hold its data contents.
The process of refreshing actually slows down the accessing of the data. An optimal cache design can minimize the delay. However, as processor speeds increase, it becomes more difficult for the cache design to compensate for the inherent slowness of the DRAM. With ever increasing operating frequency of central processing units (CPUs), conventional DRAM architectures may soon reach their practical upper limit in operating frequency and bus width.
A Direct Rambus DRAM (RDRAM) system connects one or more Direct RDRAMs together via a common bus. The bus also connects to devices such as microprocessors, digital signal processors (DSPs), graphics processors and application-specific integrated circuits (ASICs). A controller is located at one end. The RDRAMs are distributed along the bus that is connected to a Rambus channel. The bus is parallel terminated at the far end. A two-byte-wide Rambus channel uses a small number of very high speed signals to carry all address, data and control information. Therefore, in some cases, Direct RDRAMs operate at twice the bandwidth of the conventional DRAMs, such as Synchronous DRAMs (SDRAMs).
However, in order to enable fast access to data in Direct RDRAMs, the bus clock and the system clock should be accurately synchronized during high-speed operation. The clocks should also be quickly re-synchronized after power-up from a low-power mode, thus allowing the system to wake up relatively fast. Since the low-power mode, called a xe2x80x9cnapxe2x80x9d mode, is touted as a mode that allows fast wake up time (on the order of about 100 nanoseconds), a fast re-synchronization of the clocks is essential.
A phase offset between the domain clocks is determined using a sync pulse, which indicates a location of one of the domain clocks relative to other domain clocks. The domain clocks are forced into a minimum phase offset configuration by phase stalling one of the domain clocks. The phase stalling includes pushing edges of the domain clocks within a pulse width of the sync pulse. The domain clocks are then fine aligned. A signal is issued when the fine alignment is finished.